Field programmable gate arrays such as those available from Xilinx, Altera, AT&T and others are widely used for implementing various types of logic functions. FPGAs offer an advantage over mask-programmed gate arrays and discrete logic because the logic functions carried out by an FPGA can be easily reprogrammed to meet the user's objectives.
FPGAs are traditionally structured in a multi-level hierarchy, with simple logic blocks capable of performing the desired logic functions combined together to form more complex blocks, which are then combined to form a complete chip. Designs intended for implementation in FPGAs often include memories. This is especially true in prototyping applications where the designs being prototyped often contain large and complex memories.
Some FPGAs provide a mechanism for implementing small amounts of memory. For example, the Xilinx 4000 series of FPGAs allow the user to implement thirty-two bits of random-access memory ("RAM") for each configurable logic block ("CLB"). RAMs can also be constructed using the flip-flop storage elements in the CLBs. Combining these small RAMs into the larger memories found in real designs, however, is difficult, slow, and consumes much of the FPGA routing and logic resources. This problem is particularly severe when the memory to be implemented has multiple ports, especially multiple write ports which require even greater routing resources to satisfy the memory requirements. Routing of memory outputs additionally should not require a sizable expansion in the routing network. A further drawback of the existing devices is the lack of an easy way to observe the contents of the FPGA memories at a selected point in time or to initialize the memories to a predetermined state. The prior art has not effectively resolved these and other issues.